compared to the normal 8051 core:
these are in the SFR- of the core (8-bit- address), most of them are handled via the compiler
register-name | address | description | ro/rw |
---|---|---|---|
DPTR | – | data pointer (16-bit) | rw |
DPL0 | 0x82 | data pointer 0 low adress (low byte) | rw |
DPH0 | 0x83 | data pointer 0 high adress (high byte) | rw |
DPL1 | 0x84 | data pointer 1 low adress (low byte) | rw |
DPH1 | 0x85 | data pointer 1 high adress (high byte) | rw |
DPS | 0x86 | data pointer select (0 → pointer 1, 1 → pointer 2) | rw |
; assembly example ; set the first data pointer to 0x000a mov DPTR, #0x000ah ; select the second data pointer inc DPS ;set the second data pointer to 0x100a mov DPTR, #0x100ah
register-name | address | description | ro/rw |
---|
fill that out
these are located in the external RAM (16-bit- Address)
register-name | address | description | ro/rw |
---|---|---|---|
PORTACFG | 0x7f93 | 0: use port A as io 1: use special function | rw |
PORTBCFG | 0x7f94 | ” | ” |
PORTCCFG | 0x7f95 | ” | ” |
OEA | 0x7f9c | 0: input 1: output | rw |
OEB | 0x7f9d | ” | ” |
OEC | 0x7f9e | ” | ” |
PINSA | 0x7f99 | value of the input latch | ro |
PINSB | 0x7f9a | ” | ro |
PINSC | 0x7f9b | ” | ro |
//C example 1, simple assignments void main(void) { // port A and B are simple IO's (all bits are cleared) PORTACFG=0x00; PORTBCFG=0x00; // port A is input only OEA=0x00; // port B is input too but the first 4 bits are outputs OEB=0x0f; // the first 4 bits of B getting the same value as the coresponding inputs of A // the last 4 bits are of no interest OUTB=PINSA; }
//C example 2, wrong and right assignments void main(void) { // port A as IO's (all bits are cleared) PORTBCFG=0x00; // port A is output only OEB=0xff; // wrong assignment OUTC=PINSC++; // (same as PINSC=PINSC+1; OUTC=PINSC;) /* a short explanation why thats wrong the compiler would produce the following: C: PINSC=PINSC+1; ASM: mov DPTR,#PINSC movx a,@DPTR ;loading PINSC to a inc a movx @DPTR,a ;writing a to PINSC will be ignored C: OUTC=PINSC; ASM: mov DPTR,#PINSC movx a,@DPTR ;loading PINSC to a mov DPTR,#OUTC movx @DPTR,a ;writing a to OUTC */ // right assignment OUTC=PINSC+1; /* C: PINSC+1; ASM: mov DPTR,#PINSC movx a,@DPTR ;loading PINSC to a add a,#0x01 ;add 1 C: OUTC=...; ASM: mov DPTR,#OUTC movx @DPTR,a ;writing a to OUTC */ }
there are 3 16-bit timers
register-name | address | description | ro/rw |
---|---|---|---|
TCON | 0x88 | Timer 0/1 control register | rw |
TMOD | 0x89 | mode for Timer 0/1 | rw |
CKCON | 0x8e | Timer 0/1/2 Rate Control | rw |
T2CON | 0xc8 | Timer 2 control register | rw |
RCAP2L | 0xca | captured TL2 | rw |
RCAP2H | 0xcb | captured TH2 | rw |
TL2 | 0xcc | low-byte of Timer 2 | rw |
TH2 | 0xcd | high-byte of Timer 2 | rw |
bit | description | ||
---|---|---|---|
7 | GATE1, count when GATE1==0: (TR1==1) GATE1==1: (INT1==1) and (TR1==1) |
||
6 | C/T1 - Counter Timer select 0: clocked by CLK24/4 or CLK24/12 1: clocked by T1 (on high→low change) |
||
5 | M1, mode-select for Timer 1 | ||
4 | M0, mode-select for Timer 1 | ||
M1 | M0 | Mode | |
0 | 0 | mode 0: 13-bit counter | |
0 | 1 | mode 1: 16-bit counter | |
1 | 1 | mode 2: 8-bit counter with auto-reload | |
1 | 1 | mode 3: two 8-bit counters | |
3 | GATE0, count when GATE0==0: (TR0==1) GATE0==1: (INT0==1) and (TR0==1) |
||
2 | C/T0 - Counter/Timer select 0: clocked by CLK24/4 or CLK24/12 1: clocked by T0 (on high→low change) |
||
1 | M1 - mode-select for Timer 0 | ||
0 | M0 - mode-select for Timer 0 |
bit | description |
---|---|
7 | TF1 - Timer 1 overflow flag (cleared after interrupt handling) 0: ignore overflows 1: count overflows |
6 | TR1 - Timer 1 run control 0: stop Timer 1 1: run Timer 1 |
5 | TF0 - same as TF1 but for Timer 0 |
4 | TR0 - same as TR1 but for Timer 0 |
3 | IE1 - Interrupt 1 edge detect set after Interrupt 1 occured (cleared after interrupt handling) |
2 | IT1 - Interrupt 1 type select 0: detect on low level 1: detect after high→low transition |
1 | IE0 - same as IE1 but for Interrupt 0 |
0 | IT0 - same as IT1 but for Interrupt 0 |
bit | description |
---|---|
5 | T2M - Timer 2 clock select 0: clock with CLK24/12 (like normal 8051) 1: clock with CLK24/4 |
4 | T1M - same as T2M but for Timer 1 |
3 | T0M - same as T2M but for Timer 0 |
bit | description |
---|---|
7 | TF2 - Timer 2 overflow flag set when overflow from 0xffff and ( (RCLK==0) and (TCLK==0) ) has to be cleared by software |
6 | EXF2 - Timer 2 external flag set when reload or capture is caused by a high→low transition on T2EX and (EXEN2==1) |
5 | RCLK - Receive clock flag 0: Timer 1 overflow as receive clock 1: Timer 2 overflow as receive clock |
4 | TCLK - Transmit clock flag same as RCLK but for transmit clock |
3 | EXEN2 - Timer 2 external enable 0: ignore *external events on T2EX 1: enable capture or reload |
2 | TR2 - Timer 2 runt control flag 0: stop Timer 2 1: run Timer 2 |
1 | C/T2 - Counter/Timer select 0: clocked by CLK24/4 or CLK24/12 1: clocked by T2 (on high→low change) |
0 | CP/RL2 - Capture/reload flag 1 and (EXEN2==1): capture occur on high→low transistions of T2EX 0 and (EXEN2==1): auto-reload on overflow or high→low transistion on T2EX ( (RCLK==1) or (TCLK=1) )==0: ignore CP/RL2 and autoreload after each overflow |
TR2 | TCLK | RCLK | CP/RL2 | Mode |
---|---|---|---|---|
0 | X | X | X | Timer 2 stopped |
1 | 1 | X | X | Baud rate generator |
1 | X | 1 | X | Baud rate generator |
1 | 0 | 0 | 0 | 16-bit timer/counter with auto-reload |
1 | 0 | 0 | 1 | 16-bit timer/counter with capture |
X = Don't care |
//C example 1, simple setup of Timer 0 ... /* timer setup */ // Timer 0 is in mode1 (16-bit counter) TMOD=0x01; // T0M cleared -> CLK24/10 CKCON=0x00; // start Timer 0 TCON=0x10; ...
register-name | address | description | ro/rw |
---|---|---|---|
I2CS | 0x7fa5 | I2C Chip-Select | rw |
I2DAT | 0x7fa6 | I2C Data | rw |
register-name | address | description | ro/rw |
---|---|---|---|
IE | 0xa8 | Interrupt Enable | rw |
IP | 0xb8 | Interrupt Priority | rw |
EICON | 0xd8 | External Interrupt Control | rw |
EIE | 0xe8 | External Interrupt Enable | rw |
EXIF | 0x91 | External Interrupt Flag | rw |
Interrupt name | Source | Vector | Natural Priority |
---|---|---|---|
IE0 | INT0 Pin | 0x0003 | 1 |
TF0 | Timer 0 Overflow | 0x000b | 2 |
IE1 | INT1 Pin | 0x0013 | 3 |
TF1 | Timer 1 Overflow | 0x001b | 4 |
RI_0 & TI_0 | USART0 Rx & Tx | 0x0023 | 5 |
TF2 | Timer 2 Overflow | 0x002b | 6 |
Resume | WAKEUP or USB Resume | 0x0033 | 0 |
RI_1 & TI_1 | USART1 Rx & Tx | 0x003b | 7 |
USBINT | USB | 0x0043 | 8 |
PCINT | I2C Bus | 0x004b | 9 |
IE4 | INT4 Pin | 0x0053 | 10 |
IE5 | INT5 Pin | 0x005b | 11 |
IE6 | INT6 Pin | 0x0063 | 12 |
bit | description |
---|---|
7 | EA - global interrupt enable |
6 | ES1 - enable Serial Port 1 interrupt |
5 | ET2 - enable Timer 2 interrupt |
4 | ES0 - enable Serial Port 0 interrupt |
3 | ET1 - enable Timer 1 interrupt |
2 | EX1 - enable external interrupt 1 |
1 | ET0 - enable Timer 0 interrupt |
0 | EX0 - enable external interrupt 0 |
bit | description |
---|---|
7 | Reserved |
6 | Reserved |
5 | Reserved |
4 | PX6 - external interrupt 6 |
3 | PX5 - external interrupt 5 |
2 | PX5 - external interrupt 4 |
1 | PI2C - I2C Bus interrupt |
0 | PUSB - USB interrupt |
bit | description |
---|---|
7 | SMOD1 - Serial Port 1 baud rate doubler enable |
6 | Reserved |
5 | ERESI - enable Resume interrupt |
4 | RESI - Wakeup interrupt flag |
3 | INT6 - external interrupt 6 flag |
2 | Reserved |
1 | Reserved |
0 | Reserved |
bit | description |
---|---|
7 | Reserved |
6 | Reserved |
5 | Reserved |
4 | EX6 - enable external interrupt 6 |
3 | EX5 - enable external interrupt 5 |
2 | EX5 - enable external interrupt 4 |
1 | EI2C - enable I2C Bus interrupt |
0 | EUSB - enable USB interrupt |
bit | description |
---|---|
7 | IE5 - external interrupt 5 flag |
6 | IE4 - external interrupt 4 flag |
5 | I2CINT - I2C interrupt flag |
4 | USBINT - USB interrupt flag |
3 | Reserved |
2 | Reserved |
1 | Reserved |
0 | Reserved |
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