Bild: Y- Diagramm
Bild: VHDL-Entwurf
Beschreibung besteht aus mehreren Entwurfseinheiten
entity <identifier_name> [<generic_statements>] <port_signal_decleration> end [entity] [<identifier_name>];
architecture <architecture_name> of <entity_identifier> is [<decleration_ports>] begin <statement_port> end [architecture] [<architecture_name>];
configuration <configuration_name> of <identifier_name> <configuration_statements> end [configuration] [<configuration_name>];
package <package_name> is <decleration_of_exported_objects> end [package] [<package_name>];
package body <package_name> is <objects> <internal_const_types> end [package body] [<package_name>];
library <library_name> [,<library_name>];
VHDL-87 VHDL-93 7bit- ASCII 8bit-ASCII
node_a,xyz legal 12_in_bus illegal
(Zahlenbasis 2..16)
(Basiseinheit: Femtosekunde (fs)))
Klasse | Objekt | Datentyp |
---|---|---|
signal | a : | std_logic; |
a:=0.4; -- Definition einer real-Variable b:=1; -- integer-Variable
Konstante | Variable (:=) | Signal (<=) |
---|---|---|
Wert kann nur gelesen werden | Wert kann gelesen und geschrieben werden | Wert kann gelesen und neu zugewiesen werden |
nur der aktuelle Wert ist verfügbar | Zugriff ist nur auf Werte der Vergangenheit möglich Wert ist in der Zukunft zuweisbar Bsp: a<='1' after 10ns; |
signal s1 : integer range 0 to 15;
constant s2 : integer range 31 downto 0 :=0;
downto | MSB ... LSB |
to | LSB ... MSB |
* Real
signal s1 : real :=5.7E3;
clk_period : time :=50ns;
type state_type is (start,idle,wait,run); signal state : state_type; -- Mögliche FSM- Beschreibung
type bus_vector is array(7 downto 0) of std_logic;
--Speicherblock organisiert in 4 Zeilen und 2 Spalten type mem_data is array(3 downto 0,1 downto 0) of std_logic; constant rom_data : mem_data := (('0','1'),('0','0'),('1','0'),('0','1')); -- Zeile 3, ..., ..., ..., Zeile 0 -- Daten werden in FFs gespeichert, nicht im ROM! x:=rom_data(2,1); -- x:=0
-- Definition einer komplexen Zahl type complex is record real_z : integer range 0 to 31; imag_z : integer range 0 to 31; end record; -- Wertzuweisung signal val : complex; ... val.real_z<=12; val.imag_z<=25; ... -- alternativ: val<=(12,25);
-- lesen und schreiben einer Datei library ieee; use ieee.std_logig_1164.all; use ieee.std_logic_arith.all; use std.textio.all; entity textio is end entity; -- Implementierung architecture iotest of textio is begin process variable text_line,text_line_o : line; variable i1,i2,i3,sum : integer; file file_in : text is in "textio_data.in"; file file_out : text is out "./hhh/textio_data.out"; begin while not endfile(file_in) loop readline(file_in,text_line); read(text_line,i1); read(text_line,i2); read(text_line,i3); -- Aufbau "textio_data.in" -- 1 2 3 -- 4 5 6 -- 7 8 9 sum:=i1+i2+i3; write(text_line_o,string("Summe: ") ); write(text_line_o,sum); writeline(file_out,text_line_o); end loop; -- Aufbau "textio_data.out" -- Summe: 6 -- Summe: 15 -- Summe: 24 -- process würde erneut gestartet werden -- wait wartet unendlich lange wait; end process; end iotest;
subtype digit is integer range 0 to 9; -- in VHDL vordefinierte Untertypen: subtype natural is integer 0 to 2147483674; subtype positive is integer 1 to 2147483674;
Grafik: I2C Bus
Grafik: Alternative Buskonfiguration
Grafik: Aufbau eines Bustreibers
bit und bit_vector sind vordefinierte Datentypen in VHDL
mögliche Zustände 1 und 0
→ Hersteller haben eigene Typen für Tri-States
-- Aufbau 9- wertige Logik type std_ulogic is ( 'u' -- uninitialized 'x' -- forcing unknown (starker unbekannter wert, 0 und 1 zusammen) '0' -- forcing zero '1' -- forcing one 'z' -- high impedance 'W' -- weak unknown 'L' -- weak zero 'H' -- weak one '-' -- dont care );
y <= 'H' and '0'; -- y<='0';
library ieee; use ieee.std_logic_1164.all; entity stdlog is port (en1,en2,data1,data2 :in std_logic; data_bus: out std_logic); end stdlog; architecture rtl of stdlog is begin data_bus <= data1 when en1='1' else 'Z'; data_bus <= data2 when en2='1' else 'Z'; end rtl;
Grafik: Struktur
-- x1 integer range 0 to 15; -- y1 std_logic_vector (3 downto 0) y1<=conv_std_logic_vector(x1,4);
-- x2 std_logic_vector (3 downto 0) -- y2 integer range 0 to 15; y2<=conv_integer(x2);
-- Beispiel 1 <signal>' event -- Beispiel 2 <signal>' active -- true wenn Signal akiv
-- Beispiel <type_name> 'left -- liefert linke Feldnummer 'high -- Rückgabe der höchsten Feldnummer 'length -- Länge des Datentyps
if clk='1' and clk'event then ... -- Sensitivität auf steigende Taktflanke
signal a: std_logic_vector(3 downto 0); ... len:=a'length; -- len:=4
-- Teil eines Vectores ändern a_vec(4)<='1'; a_vec(3 downto 0)<="0110";
-- Zusammenhängende Zuweisung vec4(3 downto 0)<=vec8(5 downto 2); -- kürzer: vec4<='vec8(5 downto 2);
vec 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
vec 4 | 3 | 2 | 1 | 0 |
signal a: std_vector (3 downto 0); a <= (1 => '1', 3 => '1', others => '0'); -- wie: a<=''1010'';
signal a: std_vector (3 downto 0); a <= (others => '0'); -- wie: a<="0000";
x<=a nor b; x_vector <= a_vector and b_vector; --bitweise and- Verknüpfung
x | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
---|---|---|---|---|---|---|---|---|---|---|
y | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
y(7 downto 2) <= x(5 downto 0); y(1 downto 0) <= ''00''; -- Alternativ: y(7 downto 0) <= x(5 downto 0) &''00'';
architecture rtl of beispiel is -- Typ- und Signaldeklerationen für nebenläufigen Code <concurrent decleration part> begin -- (concurrent VHDL) process (...) <sequential decleration part> begin <sequential VHDL> end process; -- (concurrent VHDL) end rtl;
architecture rtl of test1 is signal a,b,c,d,e: std_logic; begin d<=a and (b or c); e<=a or b; end rtl;
architecture rtl of test1 is signal a,b,c,d,e: std_logic; begin -- process wird immer dann ausgeführt, wenn sich ein Teil der Eingänge ändert process(a,b,c) variable var: std_logic; begin var:=b or c; d<=a and var; end process; process(b,a) begin e<=a or b; end process; end rtl;
Grafik: MUX
q<=a when addr="00" else b when addr="11" else c;
q<=a when "00", b when "11", c when others;
if addr="00" then q<=a; elsif addr="11" then a<=b; else q<=c; end if;
case addr is when "00" => q<=a; when "11" => q<=b; when others => q<=c; end case;
type alu_mode is (add,sub,idle); ... variable sel: alu_mode; ... case sel is when add => c:=a+b; when sub => c:=a-b; when idle => c:=null; end case;
for i in 0 to 31 loop addr(i)<='0'; end loop;
addr(31 downto 0)<="000...000"; addr <= (others => '0');
while i<5 loop q(i)<=data_in(i); i:=i+1; end loop;
loop if i=31 then exit; else i:=i+1; q(i)<='0'; endif; end loop;
function vec2int(v:std_logic_vector) return integer variable tmp: integer :=0; begin for to i in 0 to v'range loop tmp:=tmp*2; if v(i)='1' then tmp:=tmp+1; end if; end loop; return tmp; end vec2int;
procedure vec2int (v: in std_logic_vector, f:out boolean; result: out integer) is begin result:=0; f:=true; for i in 0 to v'high loop result:=result*2; if v(i)='1' then result:=result+; f:=false; end if; end loop; end vec2int;
process(clk) begin if (clk='1' and clk'event) then q<=d; end if; end process;
process begin --Funktion prising, (Vierlogik) wait until prising(clk); q<=d; end process;
process begin -- rising_edge im Package 1164 wait until rising_edge(clk); q<=d; end process;
assert (a='1' and b='1') report "a und b nicht gleich" severity warning;
... a<='0','1' after 20ns,'0' after 30ns,'1' after 50ns,'0' after 58ns; b<='0' after 15ns; -- inertial kann auch wegegelassen werden c<=inertial aand b after 9ns; -- impuls wird unterdrückt d<=transport a and b after 12ns; ...
... architecture logiclevel of nor_gate is signal o_r: std_logic; begin y<=no(o_r); o_r<= a or b; end logiclevel;
0ns | 10ns (dt=0) | 10ns (dt=1) | 10ns (dt=2) | 20ns(dt=0) |
---|---|---|---|---|
Signalzustände | ||||
a 0 | a 1 | a 1 | a 1 | |
b 0 | b 0 | b 0 | b 0 | |
o_r 0 | o_r 0 | o_r 1 | o_r 1 | |
y 1 | y 1 | y 1 | y 0 | |
Neuberechnung o_r⇐a or b; | Neuberechnung y⇐ not(o_r); |
Welche Aktion wird ausgefhrt?
... signal x: std_logic :0; process (...) ... x<='1'; if x='1' then -- Aktion 1 else -- Aktion 2 end if; ...
→ Aktion 2 wird ausgefhrt
... process (...) variable x: std_logic:= 0; begin ... x:='1'; if (x=1) -- Aktion 1 else -- Aktion 2 end if;
→ Aktion 1 wird ausgefhrt
architecture rtl of ff1 is begin process(clk,reset) begin if (reset='0') then q<='0'; elsif (clk='1' and clk'event) then q<='d'; end if; end process; end rtl;
... architecture rtl of ff2 is begin process(rtl) begin if (clk='1' and clk'event) then if (reset='1') then q<='1'; else q<='d'; end if; end if; end process; end rtl;
architecture rtl of ff3 is begin process(clk) begin if (clk='0' and clk'event) then if (reset='0') then q<='0'; elseif (preset='0') then q<='1'; elseif (enable='1') then q<=d; else null; end if; end if; end process; end rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; enity zaehl1 is port ( clk, ld_en: in std_logic; ld: in std_logic_vector(3 downto 0); q: out std_logic_vector(3 downto 0) ); end zahl1; architecture rtl of zaehl1 is signal count: std_logic_vector(3 downto 0); begin process(clk) begin if (clk='1' and clk'event) then if (ld_en='1') then count<=ld; else count<=count+1; end if; end if; end process; q<=count; end rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use iee.std_logic.arith.all; enity zaehl1 is port ( clk, ld_en: in std_logic; ld: in std_logic_vector(3 downto 0); q: out std_logic_vector(3 downto 0) ); end zahl1; architecture rtl of zaehl2 is signal count: integer range 0 to 15; begin process(clk) begin if (clk='1' and clk'event) then if (ld_end='1') then count<=conv_integer(ld); else if (count=15) then count<=0; else count<=count+1; end if; end if; end if; end process; q<=conv_std_logic_vector(count,4); end rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; enity zaehl1 is port ( clk, ld_en: in std_logic; ld: in std_logic_vector(3 downto 0); q: out std_logic_vector(3 downto 0) ); end zahl1; architecture rtl of zaehl3 is begin process(clk) variable count: std_logic_vector(3 downto 0); begin if (clk='1' and clk'event) then if (ld_en='1') then count:=ld; else count:=count+1; end if; end if; q<=count; end process; end rtl;
library ieee; use ieee.std_logic_1164.all; entity johnson is port( clk: in std_logic; sum: out std_logic_vector(3 downto 0) ); end johnson; architecture rtl of johnson is begin process(clk) variable count: std_logic_vector (3 downto 0); begin if (clk='1' ...) then for i in 3 downto 1 loop count(i):=count(i-1); end loop; end if; sum<=count; end process; end rtl;
Q3 | Q2 | Q1 | Q0 |
---|---|---|---|
0 | 0 | 0 | 0 |
0 | 0 | 0 | 1 |
0 | 0 | 1 | 1 |
0 | 1 | 1 | 1 |
1 | 1 | 1 | 1 |
Kodierung | binär | one-hot |
---|---|---|
Anzahl | ld(n) Anzahl von Zustandsspeichern | n |
benötigter FF bei n Zuständen | mitunter kompliziert | sehr einfach |
use ieee.std_logic_1164.all; entity detect_fsm is port( x, vst, clk: in std_logic; y: out std_logic ); end detect_fsm;
architecture rtl of detect_fsm is type state_type is (z0,z1,z2,z3); signal next_state,current_state: state_type; begin next_state_process: process(current_state,x) begin case current_state is when z0 => if x='1' then next_state <= z1; end if when z1 => if x='0' then next_state <= z1; end if; when z2 => if x='0' then next_state <= z3; else next_state <= z1; end if; when others => if x='1' then next_state <= z1; else next_state <= z0; end if; end case; end process; use ieee.std_logic_1164.all; entity detect_fsm is port( x, vst, clk: in std_logic; y: out std_logic ); end detect_fsm; end process; output_process: process (current_state,x) begin if (rst='1') then current_state <= z0; elsif (clk='1' and clk'event) then current_state <= next_state; end if; end process; end rtl.
architecture rtl of detect_fsm is type state_type is (z0,z1,z2,z3); signal state: state_type; begin process(rst,clk) begin if (rst='1') then state<=z0; y<='0'; elsif (clk='1' and clk'event) then case state is when z0 => if x='1' then state <= z1; end if; when z1 => if x='0' then state <= z2; end if; y <= '0'; when z2 => if x='0' then state <= z3; else state <= z1; end if; when others => if x='1' then state <= z1; y<='1'; else state <= z0; end if; end case; endif; end process; end rtl.
architecture rtl of detect_fsm is signal z0,z1,z2,z3: std_logic; begin process (clk,rst) begin if (rst='1') then z0 <= '1'; z1 <= '0'; z2 <= '0'; z3 <= '0'; y <= '0'; elsif (clk='1' and clk'event) then z0 <= (z0 or z3) and not(x); z1 <= x; z2 <= z1 and not(x); z3 <= z2 and not(x); y <= z3 and x; endif; end process; end rtl.
library ieee; use ieee.std_logic_1164.all; entity shiftreg is port ( ld_shift,clk: in std_logic; ld_val: in std_logic_vector(4 down to 0); ser_out: out std_logic); end shiftreg; architecture rtl of shiftreg is signal tmp: std_logic_vector(4 downto 0); begin process(clk) begin if (clk='1' and clk'event) then if ld_shift='1' then tmp <= ld_val; else tmp(4 downto 0) <= tmp(3 downto 0) & '0'; endif; endif; end process; ser_out <= tmp(4); end rtl.
-A- | ||
---|---|---|
|F | |B | |
-G- | ||
|E | |C | |
-D- | ||
.H |
BCD | A | B | C | D | E | F | G | H | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |||
1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | |||
2 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | |||
3 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | |||
4 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | |||
5 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | |||
6 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |||
7 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | |||
8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
9 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
Adr[3..0] | ||||||
---|---|---|---|---|---|---|
en | div | z | d[3..0] | 1z | hex | |
0 | 0 | 0 0 | 1 1 0 0 | 0 0 | 0x30 | |
0 | 0 | 0 1 | 1 0 0 1 | 0 1 | 0x25 | |
0 | 0 | 1 0 | 0 1 1 0 | 1 0 | 0x1a | |
0 | 0 | 1 1 | 0 0 1 1 | 1 1 | 0x0f | |
0 | 1 | 0 0 | 1 1 0 0 | 0 0 | 0x30 | |
0 | 1 | 0 1 | 1 0 0 1 | 0 1 | 0x25 | |
0 | 1 | 1 0 | 0 1 1 0 | 1 0 | 0x1a | |
0 | 1 | 1 1 | 0 0 1 1 | 1 1 | 0x0f | |
Rückwärts: | ||||||
1 | 0 | 0 0 | 1 1 0 0 | 1 0 | 0x32 | |
1 | 0 | 0 1 | 1 0 0 1 | 0 0 | 0x24 | |
1 | 0 | 1 0 | 0 1 1 0 | 1 1 | 0x1b | |
1 | 0 | 1 1 | 0 0 1 1 | 0 1 | 0x0d | |
Vorwärts: | ||||||
1 | 1 | 0 0 | 1 1 0 0 | 0 1 | 0x31 | |
1 | 1 | 0 1 | 1 0 0 1 | 1 1 | 0x27 | |
1 | 1 | 1 0 | 0 1 1 0 | 0 0 | 0x18 | |
1 | 1 | 1 1 | 0 0 1 1 | 1 0 | 0x0e |
library ieee; use ieee.std_logic_1164.all; entity mux2 is port ( in0, in1, sel: in std_logic; z: out std_logic ); end mux2; architecture rtl of mux2 is begin with sel select z <= in0 when '0', in1 when others; lib... entity mux_tb is end mux_tb; architecture testbench of mux_tb is component mux2 port ( in0,in1,sel : in std_logic; z: out std_logic ); end componente; signal in0,in1,sel,z : std_logic; type sample is record in0: std_logic; in1: std_logic; sel: std_logic; end record; type sample:array is array(natural range <>) of sample; constant test_data: sample_array := (('0','0','0'),('0','0','1'),('0','1','0'), ... ,('1','1','1')); begin mux2 port map (in0 => in0, in1 => in1, sel => sel, z => z); process begin for i in test_data'range loop in0 <= test_data(i).in0; in1 <= test_data(i).in1; sel <= test_data(i).sel; wait for 10ns; end loop; wait; end process; -- Simulation bis ca. 100ns process begin wait for 5ns; assert z='0' report "wrong result" severity note; wait for 10ns; assert z='0' report "wrong result" severity note; ... wait for 10ns; assert z='1' report "wrong result" severity note; wait; end process; end;